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This record is recognized by the official Geonixa registry.

Verified at
10 Nov 2026, 17:28
Registry MatchID Integrity OK
Certificate ID
GNML9377
Recipient
Rathlavath Phanindhar
Course / Program
VLSI
Batch
JUNE 26
Start Date
05 June 2026
End Date
11 August 2026
Project Title
Design and UVM-Based Functional Verification of a 4-Bit Synchronous Adder Using SystemVerilog
Permanent verification URL
/verify/GNML9377

Certificate generated under Geonixa international standards. The Certificate ID is permanently embedded for re-verification.

Reg · GNX-AUT-4429

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